1. Field of the Invention
The present invention relates to low power autonomous peripheral circuits and methods. The novel low power autonomous peripheral circuits and methods are suitable for use in low power microprocessors, microcontrollers, or power management devices.
2. Description of the Related Art
In general, in the descriptions that follow, the first occurrence of each special term of art that should be familiar to those skilled in the art of integrated circuits (“ICs”) and systems will be italicized. In addition, when a term that may be new or that may be used in a context that may be new, that term will be set forth in bold and at least one appropriate definition for that term will be provided. In addition, throughout this description, the terms assert and negate may be used when referring to the rendering of a signal, signal flag, status bit, or similar apparatus into its logically true or logically false state, respectively, and the term toggle to indicate the logical inversion of a signal from one logical state to the other. Alternatively, the mutually exclusive boolean states may be referred to as logic_0 and logic_1. Of course, as is well known, consistent system operation can be obtained by reversing the logic sense of all such signals, such that signals described herein as logically true become logically false and vice versa. Furthermore, it is of no relevance in such systems which specific voltage levels are selected to represent each of the logic states.
Hereinafter, reference to a facility shall mean a circuit or an associated set of circuits adapted to perform a particular function regardless of the physical layout of an embodiment thereof. Thus, the electronic elements comprising a given facility may be instantiated in the form of a hard macro adapted to be placed as a physically contiguous module, or in the form of a soft macro the elements of which may be distributed in any appropriate way that meets speed path requirements. In general, electronic systems comprise many different types of facilities, each adapted to perform specific functions in accordance with the intended capabilities of each system. Depending on the intended system application, the several facilities comprising the hardware platform may be integrated onto a single IC, or distributed across multiple ICs. Depending on cost and other known considerations, the electronic components, including the facility-instantiating IC(s), may be embodied in one or more single- or multi-chip packages. However, unless expressly stated to the contrary, the form of instantiation of any facility shall be considered as being purely a matter of design choice.
Shown in FIG. 1 is a typical general purpose computer system 10. Although not all of the electronic components illustrated in FIG. 1 may be operable in the sub-threshold or near-threshold domains in any particular embodiment, some, at least, may be advantageously adapted to do so, with concomitant reductions in system power dissipation. In particular, in recently-developed battery-powered mobile systems, such as smart-phones and the like, many of the discrete components typical of desktop or laptop devices illustrated in FIG. 1 are integrated into a single integrated circuit chip. In the Related Application, I have disclosed circuits adapted to operate in the sub-threshold domain.
Shown by way of example in FIG. 2 is a typical single-chip microcontroller unit (“MCU”) 12 comprising: a central processing unit (“CPU”) 14; at least one random-access memory (“RAM”) facility 16; at least one Flash memory (“Flash”) facility 18; one or more timers (“Timers”) 20; at least one input/output master (“I/O Master”) facility 22; at least one input/output slave (“I/O Slave”) facility 24; at least one analog to digital converter (“ADC”) facility 26; a power management unit (“PMU”) 28; and a clock generator (“Clock Generator”) facility 30. A system bus (“System Bus”) 32 interconnects the several MCU facilities 14-30, and a clock distribution bus (“Clock Bus”) 34 distributes all clock signals developed by the Clock Generator 30 to the respective clocked facilities. As is known, development of the several clocks is generally controlled by information written to one or more control registers within Clock Generator 30 via the System Bus 32, and by system power state information typically provided by the PMU 28.
In low power systems, it is very desirable to have asynchronous counters, which are either driven from a clock asynchronous to the processor or are ripple counters (or both). However, it is often necessary to read these counters precisely from the processor. The counters must count correctly as the processor clock is enabled and disabled. This invention provides a method for resolving all of these issues.
FIG. 3 illustrates, in block diagram form, a typical timer facility configuration The timer is an N-bit counter which may be loaded with some initial value (possibly only zero) by software, and which then counts clock pulses from a selected clock source. It is desirable that the value in the Timer may be read via software at any time, even when the Timer is being clocked. The CPU Bus Interface is clocked on the system clock BCLK, and the data from the Timer must be supplied to it synchronously. If Clock1, Clock2, and Clock3 are all generated synchronously to BCLK, i.e. from the same source clock, this system will work correctly because the Timer will change synchronously to the read clock BCLK. This assumes that the Timer is implemented as a synchronous counter.
In systems which are focused on low power, there are often two factors which introduce difficulties into the above architecture. The first factor is that the source clocks for the various timer clocks, Clock1, Clock2, and Clock3, may not be the same as the source clock which creates BCLK. This may be because, for example, the Timer requires a more accurate clock, such as one generated from a Crystal Oscillator, while the source of BCLK is a less accurate but higher frequency RC Oscillator. It may also be because the source oscillator for BCLK is a high power device and the Timer can use a much lower frequency and much lower power source oscillator. The result of this architecture is that Clock1, Clock2, and Clock3 may not be synchronous to BCLK. The second factor is that for low power, the system must be able to stop the system clock BCLK, and enter a low power state typically referred to as “sleeping”. However, the Timer clocks must continue to run even when the system is sleeping, and no clock pulses to the Timer can be added or dropped as the system moves between “sleeping” states where BCLK is not active and “running” states where BCLK is active.
These two requirements make reading the Timer correctly in every situation challenging. The prior art has handled this in several ways. The first way is to simply admit that precise reads are not possible, and require software to read the Timer multiple times until a value is read which is believed to be consistent. For low frequency timer clocks this is a workable but adds some software complexity. If the Timer clock frequency is in the same range as the frequency of BCLK, it may take a number of reads in order to produce a valid result. The second way is to require the source oscillator of BCLK to run at all times that the Timer is being clocked, even if the system is in a “sleeping” power state. In that case the Timer clock can be synchronized to the system clock at all times and reliable reads are possible. However, the high frequency source oscillator is often a major contributor to system power, and requiring it to remain active at all times can impose a significant power penalty. FIG. 4 illustrates, in block diagram form, a clock synchronization facility. This illustration shows Sync_clk is the always-running clock synchronous to BCLK. The selected source clock is synchronized in 2 flip-flops so the Clk_out is a stable clock of the same frequency as Clk_int. Note that in this implementation Clk_int must be no more than ½ of the frequency of Sync_clk.
What is needed is a method and apparatus adapted to provides a mechanism for clocking the Timer in such a way that a single read is always guaranteed to be correct but does not require the clock source oscillator to be active in “sleeping” power states, while consuming less power than known prior art.